FIG. 1 shows a simplified representation of a design flow 100 for the design, verification and manufacture of integrated circuits (chips). Many of the operations in the design flow 100 are performed using computer-implemented tools, including computer-aided design (CAD) tools. Many of the operations are implemented in software, the software running on hardware servers and workstations.
In a design specification document 110, parameters for a chip design or semiconductor product are listed, and characteristics such as function, speed, power consumption, noise levels, signal quality, cost, etc. are described.
In a circuit implementation operation 120 a semiconductor circuit is generated (i.e., one or more circuit designs for the circuit are generated) based on the information in specification document 110. For ease of explanation and discussion, in the following discussion the terms “circuit” and “semiconductor circuit” shall be understood to mean the design (e.g., netlist and/or physical layout) of the circuit, as opposed to a physical circuit that physically conducts currents and signals. EDA tools are commonly used to generate the detailed design of a semiconductor circuit. In a system specification operation 122, the design parameters 110 for the semiconductor circuit, including an interface to a system, are provided to one or more EDA tools. The design parameters are later checked against a completed semiconductor circuit. In a circuit design and test operation 124, a circuit implementing the system specification 122 is generated manually (known as a “custom” or “full custom” design), or automatically by a compiler tool, using ready-made IP functions, etc., or by using a combination of these operations. In a custom design, the circuit is entered by schematic capture, by a hardware description language (such as Verilog, VHDL, or any other hardware description language (HDL)), by graphic entry, or by other means. In a circuit synthesis operation 126, a netlist of the circuit is generated by synthesizing the circuit design 124 into a gate-level representation of the circuit design. Synthesis is generally performed only on synthesizable logic sections of the circuit 124, in a logic synthesis operation. If the circuit 124 includes a section that cannot be synthesized (e.g., an analog block), that section of the circuit may be called a non-synthesizable section. In logic synthesis an abstract form of desired circuit behavior (typically a register transfer level (RTL) description or behavioral description) is turned into a design implementation in terms of logic gates. In a verification operation 128, the netlist output by the circuit synthesis operation 126 is verified for functionality against the circuit design 124, and optionally against the desired system specification 122, using a test-bench program or test vectors. The operations 124, 126, and 128 are repeated until the netlist meets the desired parameters.
In a floorplanning and layout operation 130, a physical implementation of the netlist on a physical medium, such as a die on a semiconductor wafer, is specified. In an analysis operation 132, a transistor-level simulation of the netlist 126 is performed to verify functionality, timing, and performance across predefined or user-specified ranges of process, voltage, and temperature parameters. In a physical verification operation 134, the physical implementation 130 is analyzed for parasitic effects such as parasitic capacitance, inductance, resistance, and other effects. The physical implementation is verified to make sure it does not violate design rules for the semiconductor process on which the integrated circuit will be manufactured. Operations 130, 132, and 134 are repeated until the physical implementation (i.e., a specification of the physical implementation) meets desired parameters. In a mask preparation operation 136, optical pattern data (commonly called “mask data”) is generated from the physical implementation for use on a photolithographic mask.
In a tape-out operation 140, the optical pattern data 136 is written to a magnetic tape (this process is called “tape out”) and/or sent to a semiconductor wafer manufacturer by physical or electronic means. In an operation 150, the semiconductor wafer manufacturer uses the optical pattern data 136 to generate photolithographic masks. These photolithographic masks are then used by a wafer fabricator to manufacture semiconductor wafers. In saw operation 160, the manufactured semiconductors wafers are sawn into individual dice, in a die separation process. The individual dice are then assembled into individual packages and tested. Optionally, preliminary testing of the individual die may be performed before the wafers are sawn into individual dice, thereby identifying die which may be discarded prior to additional investment of testing and assembly resources. In operation 170, the packaged integrated circuits are prepared for sale.